1. Field
The invention relates to the testing of memory circuits.
2. Background Information
During the course of operation computer systems may perform procedures known as power on self test (POST) and boot. A computer system is any device comprising a processor and a memory to store instructions and data to be supplied to the processor. Typically, the processor and memory are coupled by way of one or more busses. Booting is typically accomplished by either powering on the computer system, or resetting the computer system to an initial state. A POST may then be performed to diagnose and initialize resources, such as random access memory (RAM), before transferring control to the computer system""s basic input/output system (BIOS).
Diagnosing memory may be complicated by the presence of cache memories. A cache memory is any memory which operates to store a copy of the contents of a larger, slower memory. The operation and benefits of cache memories are well known in the art. During POST, data values may be read and written to memory. A pre-selected data pattern may be written to a memory region to test and then read back. The data pattern written is compared with the data pattern read to verify the read-write operation of the memory. When the memory cache is present and enabled, write operations to the memory may modify ranges of the cache memory, not the memory to which the write operation is addressed. Likewise, read operations from the memory may result in the reading of data from regions of cache memory and not from the memory regions addressed. Consequently, operation of the memory regions may not be properly validated during POST.
Prior art approaches to this problem have taken the approach of disabling cache memory before writing the test pattern to and reading it back from the memory region to test. However, the performance benefits associated with enabling cache memory are lost under these approaches.
In one aspect, a method includes filling a cache memory with a test pattern and forcing a write-back of the cache memory to a region of memory. The cache memory is refilled with the contents of the region of memory, and the contents of the cache memory are compared with the test pattern.